PIC16C63A-04I/SO【PDF 139/184 页】IC MCU OTP 4KX14 PWM 28SOIC

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Sheet目录3841

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SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

13.3

Functional Description

13.3.1

Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State

Manager. It runs at Slow Clock and generates the following reset signals:

proc_nreset: Processor reset line. It also resets the Watchdog Timer.

periph_nreset: Affects the whole set of embedded peripherals.

nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on software action. The

Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an

assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device

resets.

The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator

startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical

Characteristics section of the product documentation.

13.3.2

NRST Manager

The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Man-

ager. Figure 13-2 shows the block diagram of the NRST Manager.

Figure 13-2. NRST Manager

13.3.2.1

NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is

reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writ-

ing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin

NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.

The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the

bit URSTIEN in RSTC_MR must be written at 1.

External Reset Timer

URSTS

URSTEN

ERSTL

exter_nreset

URSTIEN

RSTC_MR

RSTC_SR

NRSTL

nrst_out

NRST

rstc_irq

Other

interrupt

sources

user_reset

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